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Communications receiver architectures and algorithms permitting hardware adjustments for optimizing performance

机译:通信接收器体系结构和算法允许进行硬件调整以优化性能

摘要

A receiver architecture featuring a decimation filter and a bypass around said decimation filter is disclosed along with a method for optimizing said receiver's sampling phase and programmable gain amplifier. Said method utilizes said receiver architecture to modify said receiver's receive path to simplify optimizations.
机译:公开了一种具有抽取滤波器和围绕所述抽取滤波器的旁路的接收机架构,以及用于优化所述接收机的采样相位和可编程增益放大器的方法。所述方法利用所述接收器架构来修改所述接收器的接收路径以简化优化。

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