首页> 外国专利> PATTERN GENERATING METHOD FOR BURST ERROR AND DETECTION /CORRECTION APPARATUS FOR BURST ERROR AND BYTE ERROR

PATTERN GENERATING METHOD FOR BURST ERROR AND DETECTION /CORRECTION APPARATUS FOR BURST ERROR AND BYTE ERROR

机译:突发错误的图形生成方法及突发错误和字节错误的检测/校正装置

摘要

PROBLEM TO BE SOLVED: To detect burst errors and byte errors in reception information, and to correct them in parallel. ;SOLUTION: A syndrome S is determined from reception information D and a parity inspection matrix for correcting a burst error, having a length up to b bits. the syndrome S is inputted into burst error pattern generating circuits 2-1 through 2-p which overlap by b-1 bits with each other, with each having information framework of 2b-bit length. If the burst error is contained completely in the framework of one of the circuits 2-1 through 2-p, this burst error pattern is outputted. An error pattern calculating circuit 3 takes logical OR with an overlapping part from the outputs of the circuits 2-1 through 2-p. Exclusive OR of the output of the circuit 3 and the information D is taken, to obtain a correction information DS. Thus, burst error in the information D can be detected and corrected.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:检测接收信息中的突发错误和字节错误,并进行并行纠正。 ;解决方案:从接收信息D和用于校正突发错误的奇偶校验矩阵确定校正子S,其长度不超过b位。将校正子S输入到突发错误码型产生电路2-1至2-p,该电路彼此重叠b-1个比特,每个都具有2b比特长的信息框架。如果突发错误完全包含在电路2-1至2-p之一的框架中,则输出该突发错误模式。误差模式计算电路3从电路2-1至2-p的输出取逻辑“或”与重叠部分。取电路3的输出与信息D的异或,以获得校正信息DS。因此,可以检测并纠正信息D中的突发错误。;版权所有:(C)2003,JPO

著录项

  • 公开/公告号JP2002374175A

    专利类型

  • 公开/公告日2002-12-26

    原文格式PDF

  • 申请/专利权人 FUJIWARA EIJI;FANUC LTD;

    申请/专利号JP20010180455

  • 发明设计人 KINOSHITA JIRO;FUJIWARA EIJI;

    申请日2001-06-14

  • 分类号H03M13/17;G06F11/10;G11B20/18;H04L1/00;

  • 国家 JP

  • 入库时间 2022-08-22 00:13:09

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