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Breakdown simulation manner and failure analysis manner null of large-scale integration

机译:大规模集成的故障模拟方式和故障分析方式无效

摘要

PROBLEM TO BE SOLVED: To reduce time for fault simulation and at the same time perform a fault analysis based on a fault dictionary that is created by the fault simula tion easily in a large-scale integrated circuit device where an internal total mega cell can be tested easily. ;SOLUTION: The fault simulation of a large-scale integrated circuit device is performed by dividing into a path from each terminal of each mega cell to the external terminal of the large-scale integrated circuit device and a peripheral circuit other than the mega cell, first, second, and third fault dictionaries 110, 104, and 112 where each result information is registered are created, and the fault detection rate of an entire large-scale integrated circuit device is calculated based on it. Also, the information of the fault dictionaries 110, 104, and 112 is compared with the information of the fail result of a tester for testing the large-scale integrated circuit device, thus locating the failed part of the large-scale integrated circuit device.;COPYRIGHT: (C)1998,JPO
机译:解决的问题:减少故障仿真的时间,同时基于故障字典执行故障分析,该故障字典可在大型内部集成大型单元的集成电路设备中轻松地通过故障仿真创建。测试容易。 ;解决方案:大型集成电路设备的故障仿真是通过划分从每个大型单元的每个端子到大型集成电路设备的外部端子以及大型单元以外的外围电路的路径来进行的,创建登记了每个结果信息的第一,第二和第三故障字典110、104和112,并据此计算整个大型集成电路装置的故障检测率。另外,将故障字典110、104和112的信息与用于测试大型集成电路装置的测试器的故障结果的信息进行比较,从而定位大型集成电路装置的故障部分。 ;版权:(C)1998,日本特许厅

著录项

  • 公开/公告号JP3428313B2

    专利类型

  • 公开/公告日2003-07-22

    原文格式PDF

  • 申请/专利权人 株式会社東芝;

    申请/专利号JP19960260024

  • 发明设计人 新 田 進;

    申请日1996-09-30

  • 分类号G01R31/28;G01R31/3183;G06F11/26;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:21:45

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