首页>
外国专利>
Breakdown simulation manner and failure analysis manner null of large-scale integration
Breakdown simulation manner and failure analysis manner null of large-scale integration
展开▼
机译:大规模集成的故障模拟方式和故障分析方式无效
展开▼
页面导航
摘要
著录项
相似文献
摘要
PROBLEM TO BE SOLVED: To reduce time for fault simulation and at the same time perform a fault analysis based on a fault dictionary that is created by the fault simula tion easily in a large-scale integrated circuit device where an internal total mega cell can be tested easily. ;SOLUTION: The fault simulation of a large-scale integrated circuit device is performed by dividing into a path from each terminal of each mega cell to the external terminal of the large-scale integrated circuit device and a peripheral circuit other than the mega cell, first, second, and third fault dictionaries 110, 104, and 112 where each result information is registered are created, and the fault detection rate of an entire large-scale integrated circuit device is calculated based on it. Also, the information of the fault dictionaries 110, 104, and 112 is compared with the information of the fail result of a tester for testing the large-scale integrated circuit device, thus locating the failed part of the large-scale integrated circuit device.;COPYRIGHT: (C)1998,JPO
展开▼