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MATRIXADRESSIBLE NOTIFICATE WITH EXCHANGE OF AID FOR A PROCESSING SCHEME

机译:可交换处理方案的矩阵可通知通知

摘要

A matrix addressable display includes a delay locked loop formed from a delay chain formed from several variable delay blocks and a comparator. The delay locked loop receives a horizontal sync portion of an image signal and propagates the horizontal sync through the chain of delay blocks. The output of the last delay block drives the comparator that also receives an undelayed horizontal sync component. The comparator compares the undelayed horizontal sync to the delayed horizontal sync component and produces an error signal corresponding to the phase difference. The error signal is input to each of the delay blocks. In response to the error signal, the delay of the respective delay blocks increases or decreases to reduce the phase difference between the undelayed horizontal sync component and the delayed sync component. In addition to driving the delay chain, the horizontal sync component also walks a "1" through a row driver to sequentially activate rows of the array.
机译:矩阵可寻址显示器包括由多个可变延迟块形成的延迟链形成的延迟锁定环和比较器。延迟锁定环接收图像信号的水平同步部分,并通过延迟块链传播水平同步。最后一个延迟块的输出驱动比较器,该比较器还接收无延迟的水平同步分量。比较器将未延迟的水平同步与延迟的水平同步分量进行比较,并产生与相位差相对应的误差信号。误差信号被输入到每个延迟块。响应于误差信号,各个延迟块的延迟增大或减小,以减小未延迟的水平同步分量和延迟的同步分量之间的相位差。除了驱动延迟链之外,水平同步组件还通过行驱动器传递“ 1”以顺序激活阵列的行。

著录项

  • 公开/公告号DE69710085D1

    专利类型

  • 公开/公告日2002-03-14

    原文格式PDF

  • 申请/专利权人 MICRON TECHNOLOGY INC.;

    申请/专利号DE19976010085T

  • 发明设计人 HUSH E.;

    申请日1997-10-03

  • 分类号G09G3/20;

  • 国家 DE

  • 入库时间 2022-08-22 00:25:00

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