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Device for manipulating address information in a memory tester controls address channels in the memory tester with address registers storing logical address bits, replacement bits, a bit selector and a vector processor.
Device for manipulating address information in a memory tester controls address channels in the memory tester with address registers storing logical address bits, replacement bits, a bit selector and a vector processor.
A memory tester has a feature for using any section of a z address register as a substitute for up to eight most significant bits in x address lines. A majority of z selection multiplexers select one of sixteen z address lines for transfer to a majority of z-bit activation multiplexers. Each z-bit activation multiplexer chooses between a selected z-bit or a matching x address bit. An Independent claim is also included for a method for manipulating address information in a memory tester.
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