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VHDL Random Interleaver Achitecture Used VHDL
VHDL Random Interleaver Achitecture Used VHDL
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机译：VHDL随机交织器架构使用的VHDL
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摘要
PURPOSE: A design for a random interleaver using VHDL is provided to perform efficiently a data distribution process by forming the random interleaver. CONSTITUTION: A random interleaver is formed by storing progression generated from a random progression generator. An arrangement for interleaving is stored into a ROM. The random interleaver is formed by using a lookup table. The random progression is obtained by receiving time information of 4 bits. A ROM-table is generated by VHDL. The random progression is stored in the ROM-table. An interleaving process is performed according to a stored pattern of the ROM-table when encoded data are inputted from input data of 4 bits selected by a selection terminal of a Mux. The random progression for recovering the original data of the interleaver. The random progression is stored in a ROM-table of a deinterleaver. A deinterleaving process is performed according to the stored pattern of the ROM-table.
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