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PLL FREQUENCY SYNTHESIZER AND METHOD FOR CONTROLLING THE PLL FREQUENCY SYNTHESIZER
PLL FREQUENCY SYNTHESIZER AND METHOD FOR CONTROLLING THE PLL FREQUENCY SYNTHESIZER
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机译：锁相环频率合成器和控制锁相环频率合成器的方法
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摘要
A PLL frequency synthesizer is provided with: a voltage detector (9) for detecting the current value of a control voltage to be applied to a voltage-controlled oscillator (6); a storage device (7) which has prestored therein a plurality of set values of control voltages corresponding to a plurality of set values of frequency dividing numbers to be set in a frequency divider (2) and which selects that one of the plurality of set values of control voltages which corresponds to the frequency dividing number set in the frequency divider; voltage value comparator (8) for comparing the current value of the control voltage detected by the voltage detector (6) and the set value of the control voltage output from the storage device (7); and a switching circuit (10) whereby a phase difference signal indicative of the phase difference between a frequency-divided signal from the frequency divider (2) and a reference frequency signal, generated by a phase comparator (3), and the output signal from the voltage value comparator (8) are selectively switched for application to a charge pump (4). The voltage value comparator (8) controls the switching circuit (10) to drive the charge pump (4) by the output signal from the comparator itself when the difference between the detected current value of the control voltage and the set value of the control voltage read out of the storage device (7) is greater than a predetermined value, and at all other times, by the phase difference signal from the phase comparator (3).
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