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Delay computation apparatus, delay computation method, and storage medium for determining a path of a logic circuit with maximum or minimum delay times
Delay computation apparatus, delay computation method, and storage medium for determining a path of a logic circuit with maximum or minimum delay times
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机译：用于确定具有最大或最小延迟时间的逻辑电路的路径的延迟计算设备，延迟计算方法和存储介质
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摘要
An apparatus of the present invention computes delay times of logic paths included in a logic circuit which has a plurality of elements whose output is determined by the input of a clock signal and at least one signal which is not the clock signal. The apparatus includes: a first element which stores information about the logic circuit; a second element which groups pairs of two elements into groups based on a clock skew range value between the elements in each of the pair groups; and a third element which computes a delay time for each of the groups grouped by the second element by using a predetermined clock skew value related to the range used in the second element and the information about the logic circuit stored in the first element.
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