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Dual threshold delay measurement/scaling scheme to avoid negative and non-monotonic delay parameters in timing analysis/characterization of circuit blocks
Dual threshold delay measurement/scaling scheme to avoid negative and non-monotonic delay parameters in timing analysis/characterization of circuit blocks
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机译：双阈值延迟测量/缩放方案，可避免电路块时序分析/特征化中出现负和非单调延迟参数
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摘要
Timing characterization/analysis of a number of circuit blocks of a library or an integrated circuit, where each circuit block has an associated rise threshold value and fall threshold value, is performed using a common rise voltage threshold value equal to a minimum one of the rise threshold values of all the circuit blocks and a common fall threshold value equal to a maximum one of the fall threshold values of all the circuit blocks. The rise threshold value of each of the circuit blocks may be determined through an iterative process in which a new rise threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold. Similarly, the fall threshold value of each of the circuit blocks may be determined through an iterative process in which a new fall threshold is determined for an input corresponding to an output threshold value equal to the previous rise or fall threshold. These iterative processes may be repeated until the new rise and/or fall threshold is within a required tolerance value of the preceding rise and/or fall threshold.
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