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Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length
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机译：形成具有基本相同的小于0.25微米栅极长度的CMOS晶体管的双隔离层方法
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摘要
CMOS transistors, i.e., N- and P-type transistors, are formed with substantially the same gate length and source/drain regions with lightly doped extensions. Embodiments include sequentially: ion implanting an N-type impurity, e.g. As, to form the N- type transistor shallow source/drain implants; forming relatively thin first sidewall spacers on the gates of both transistors; ion implanting a P-type impurity, e.g. BF2, to form shallow source/drain extension implants for the P-type transistor; forming relatively thick side wall spacers on the first sidewall spacers of both transistors; ion implanting, e.g. As, to form moderately or heavily doped N-type implants; activation annealing at a first temperature, e.g., about 1050° C. to form the shallow N- and P-type source/drain extensions and moderately or heavily doped P-type source/drain regions; ion implanting a P-type impurity, e.g., BF2, to form moderately or heavily doped P-type source/drain implants; and activation annealing at a second temperature less than the first temperature, e.g., at about 1000° C. to form moderately or heavily doped P type source/drain regions.
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