首页>
外国专利>
Balanced-delay programmable logic array and method for balancing programmable logic array delays
Balanced-delay programmable logic array and method for balancing programmable logic array delays
展开▼
机译：平衡延迟可编程逻辑阵列和用于平衡可编程逻辑阵列延迟的方法
展开▼
页面导航
摘要
著录项
相似文献
摘要
Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.
展开▼
