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Methods and systems for testing integrated circuit memory devices by overlappiing test result loading and test result analysis

机译:通过重叠加载测试结果和测试结果分析来测试集成电路存储器件的方法和系统

摘要

Integrated circuit memory devices are tested by loading into a first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Automatic switching then takes place to a second defect interpretation memory. The results of a succeeding comparison test are loaded therein, while simultaneously analyzing results from the preceding comparison test in the first defect interpretation memory. Then, automatic switching back to the first defect interpretation memory takes place, and results of a next succeeding comparison test are loaded therein while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory. Automatic switching and automatic switching back are repeatedly performed, to thereby simultaneously test a memory device and analyze memory test results.
机译:通过将第一存储装置中输入的测试图案数据和从存储装置输出的结果数据之间的先前比较测试的结果加载到第一缺陷解释存储器中,来测试集成电路存储装置。然后自动切换到第二个缺陷解释存储器。将随后的比较测试的结果加载到其中,同时在第一缺陷解释存储器中同时分析来自先前的比较测试的结果。然后,自动切换回第一缺陷解释存储器,并且在第二缺陷解释存储器中同时分析来自随后的比较测试的结果的同时,将下一个随后的比较测试的结果加载到其中。重复执行自动切换和自动切回,从而同时测试存储器设备并分析存储器测试结果。

著录项

  • 公开/公告号US6288955B1

    专利类型

  • 公开/公告日2001-09-11

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号US19990415523

  • 发明设计人 KI-SANG KANG;KAZUHIRO SHIBANO;

    申请日1999-10-08

  • 分类号G11C70/00;

  • 国家 US

  • 入库时间 2022-08-22 01:03:19

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