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Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system
Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system
A distributed address mapping and routing technique supports flexible configuration and partitioning in a modular, shared memory multiprocessor system having a plurality of multiprocessor building blocks interconnected by a switch fabric. The technique generally employs physical-to-logical address translation mapping in conjunction with source routing. Mapping operations, such as address range or processor identifier operations, used to determine a routing path through the switch fabric for a message issued by a source multiprocessor building block are resolved through the generation of a routing word. That is, each message transmitted by a source multiprocessor building block over the switch fabric has an appended routing word that specifies the routing path of the message through the fabric.
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