首页> 外国专利> Assessing plasma induced gate dielectric degradation with stress induced leakage current measurements

Assessing plasma induced gate dielectric degradation with stress induced leakage current measurements

机译:通过应力感应泄漏电流测量评估等离子体感应栅极介电质的退化

摘要

Plasma induced degradation of thin gate dielectric layers, e.g. , silicon dioxide layers of less than 50 Å, is assessed by impressing a constant current density across the gate dielectric layer and measuring the resulting stress induced leakage current as a function of time. The sensitivity of the stress induced leakage current to traps generated in a thin gate dielectric layer enables the use of stress induced leakage current measurements to monitor plasma induced damage during various phases of semiconductor manufacturing.
机译:等离子体引起的薄栅极介电层的降解,例如通过在栅极介电层上施加恒定的电流密度并测量所产生的应力引起的漏电流随时间的变化,可评估小于50的二氧化硅层。应力引起的泄漏电流对在薄栅极介电层中产生的陷阱的敏感性使得能够使用应力引起的泄漏电流测量来监视半导体制造的各个阶段期间的等离子体引起的损坏。

著录项

  • 公开/公告号US6043102A

    专利类型

  • 公开/公告日2000-03-28

    原文格式PDF

  • 申请/专利权人 ADVANCED MICRO DEVICES INC.;

    申请/专利号US19970924129

  • 发明设计人 PENG FANG;JIANG TAO;

    申请日1997-09-05

  • 分类号H01L21/66;

  • 国家 US

  • 入库时间 2022-08-22 01:37:32

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