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Evaluation system for large-scale integrated circuits uses a CAD logic process with the test circuit layout data to generate data for comparison with data arising from input of test data from a test data file
Evaluation system for large-scale integrated circuits uses a CAD logic process with the test circuit layout data to generate data for comparison with data arising from input of test data from a test data file
System comprises a test data file for storage of a test pattern, which is applied to the device under test as well as a theoretical value pattern which is to be compared with the output signal generated by the test circuit in response to the input test pattern. The device also comprises an event data store for storage of data from the test component and a certain part of the test pattern from the test file, a FIFO (first in first out) unit which processes event data from the test device in the same sequence as it is received, a second data store for storage of logic simulation data arising from a CAD process carried out with test component layout data, a second FIFO unit for processing this data sequentially and a comparator for producing a comparison result of the data from the 2 FIFO units. Means is provided for generation of a comparison result.
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