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Vertical IC, e.g. a vertical integrated CMOS circuit, comprises a chip stack with a via which electrically connects metallizations of spaced-apart chips and which is insulated from an intermediate chip
Vertical IC, e.g. a vertical integrated CMOS circuit, comprises a chip stack with a via which electrically connects metallizations of spaced-apart chips and which is insulated from an intermediate chip
A vertical IC, comprising a chip stack (30) with a via (25b) which electrically connects metallizations (4, 21) of spaced-apart chips (2, 19) and which is insulated from an intermediate chip (8), is new. A vertical IC comprises (a) a stack (30) of first, second and third circuit chips (2, 8, 19), each having a circuit structure (3, 9, 20) and a metallization structure (4, 10, 21); and (b) a via (25b) which extends between and electrically connects the first chip and third chip metallization structures (4, 21) and which is electrically insulated from the second chip (8). An Independent claim is also included for production of the above vertical IC.
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