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PATTERN FOR EXAMINATION AND EXAMINATION METHOD THEREFOR

机译:考试模式及考试方法

摘要

PROBLEM TO BE SOLVED: To easily detect defects such as short circuitting of a contact hole for making a semiconductor substrate conduct with other wiring, with a conductive pattern which originally is not conducted. SOLUTION: A pattern for examination formed on a silicon substrate 21 is provided with a first contact line composed of plural polysilicon wiring layers 104 insulated from the silicon substrate 21 and plural contact holes 101 arranged, corresponding to the polysilicon wiring layers 104, conducted to the silicon substrate 21 and insulated from the polysilicon wiring layers 104 via a sidewall 24 and a second contact line composed of plural contact hole 102 arranged corresponding to the polysilicone wiring layers 104 and respectively conducted to the respective correspondent polysilicon wiring layers 104.
机译:解决的问题:为了容易地检测诸如使半导体衬底与其他布线导电的接触孔短路之类的缺陷,其具有最初不导电的导电图案。解决方案:在硅基板21上形成的检查图案具有第一接触线,该第一接触线由与硅基板21绝缘的多个多晶硅布线层104和与该多晶硅布线层104相对应布置的多个接触孔101构成,硅基板21并通过侧壁24和第二接触线与多晶硅布线层104绝缘,该侧壁24和第二接触线由与多晶硅布线层104相对应布置并分别导通到相应的相应多晶硅布线层104的多个接触孔102组成。

著录项

  • 公开/公告号JP2000208581A

    专利类型

  • 公开/公告日2000-07-28

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19990003773

  • 发明设计人 NISHIO NAOHARU;

    申请日1999-01-11

  • 分类号H01L21/66;G01R31/02;H01L21/28;H01L21/3065;H05K3/00;

  • 国家 JP

  • 入库时间 2022-08-22 02:00:46

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