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Radiation-hard isoplanar cryo-CMOS process suitable for sub- micron devices
Radiation-hard isoplanar cryo-CMOS process suitable for sub- micron devices
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机译：适用于亚微米设备的辐射硬等平面冷冻CMOS工艺
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摘要
A radiation-hard isoplanar cryo-CMOS process suitable for submicron device fabrication reduces channel length to submicron levels. A channel stop (52) is formed after a first polysilicon gate (50) is formed to reduce the space between a n-/n+ source/drain region (67, 68) and the channel-stop region (52). Double gate oxidation steps are performed to increase polyoxide thickness. A thermal oxide masking step is carried out to obtain a thin layer of gate oxide under a second polysilicon gate (60A) for CMOS devices. The process includes two different second polysilicon masking steps to provide dimension control of second polysilicon gates (60A) and to remove bridging of the second polysilicon where the second polysilicon layer (58) is over the first polysilicon layer (48).
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机译：适用于亚微米设备制造的辐射硬等平面低温CMOS工艺将沟道长度减小到亚微米水平。在形成第一多晶硅栅极（50）之后形成沟道停止层（52），以减小n- / n +源极/漏极区域（67、68）和沟道停止区域（52）之间的空间。执行双栅极氧化步骤以增加多氧化物的厚度。进行热氧化物掩模步骤以获得在用于CMOS器件的第二多晶硅栅极（60A）下面的栅极氧化物的薄层。该工艺包括两个不同的第二多晶硅掩模步骤，以提供第二多晶硅栅极（60A）的尺寸控制并去除第二多晶硅的桥接，其中第二多晶硅层（58）在第一多晶硅层（48）上方。
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