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Control circuit in a Universal Asynchronous Receiver / Transmitter (UART) half duplex bidirectional Wireless One Channel; Universal Asynchronous Receiver / Transmitter (UART)And method of operation
Control circuit in a Universal Asynchronous Receiver / Transmitter (UART) half duplex bidirectional Wireless One Channel; Universal Asynchronous Receiver / Transmitter (UART)And method of operation
It includes a logical unit in which the "four groups" of receiving ports are processing the data transmitted by wireless. More specifically, a logical unit is connected to a data storage, a FIFO transmission log station, a fourth processor and an external processor, wherein the logical unit analyzes the state of each Lassana from each designated connection point,In addition, a novel method is also disclosed in which the logical unit allows the receiver to receive data only when the data developer is empty, the drive recording board is empty, and the authority indicator of the receiver is empty. If the external CPU has specified the half dual function release mode, it is valid. Otherwise, the logical unit can only give the receiving human rights when it specifies the processability of the second function and places the allocation index of the receiver in the logical unit.
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