首页>
外国专利>
Multiplexer comprising an N-stage shift register with each stage composed of a dual output D F/F with one output used for multiplexing and the other for next stage
Multiplexer comprising an N-stage shift register with each stage composed of a dual output D F/F with one output used for multiplexing and the other for next stage
展开▼
机译：多路复用器，包括一个N级移位寄存器，每个级由一个双路输出D F / F组成，一个输出用于多路复用，另一路用于下一级
展开▼
页面导航
摘要
著录项
相似文献
摘要
For time division multiplexing N bit-parallel circuit input signals at a high bit rate such as higher than 2.4 Gb/s, where N represents a predetermined integer greater than one, a multiplexer circuit comprises an N-stage shift register (11) for shifting a signal pulse through first to N-th dual output D F/F's (11(1)-11(N)) to produce N master and slave output signals as N stage output signals, N two-input NAND gates (15(1)- 15(N)) supplied with the N bit parallel circuit input signals and the N master output signals to produce N gate output signals, an N-input NAND gate (17) multiplexing the N gate output signals into a single gate output signal, and a retiming D F/F (19) for retiming the single gate output signal into a bit-serial circuit output signal. The N slave output signals are delivered respectively to the dual output D F/F's of next stages. Each master output signal is produced by a slave input transfer gate (37) in each dual output F/F comprising master and slave latches master-slave connected together. Preferably, the signal pulse is a negative going pulse. NOR gates may be used instead of the NAND gates.
展开▼
