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Trellis demapper of a convolutional decoder for decoding pragmatic trellis codes suitable for use in a multi-channel receiver of satellite, terrestrial and cable transmitted FEC compressed-digital television data
Trellis demapper of a convolutional decoder for decoding pragmatic trellis codes suitable for use in a multi-channel receiver of satellite, terrestrial and cable transmitted FEC compressed-digital television data
A memory efficient trellis demapper for demapping 8-PSK and 16, 32, 64 128 and 256-QAM trellis codes contains respective I-channel, Q- channel and remapper random access memory (RAM), an 8-PSK demapper logic network, and a selector switch. Each RAM includes a lookup table selectively programmed for each QAM code. The I-channel RAM and the Q- channel RAM forward their respective outputs through the switch as the trellis demapper output in response to an even power of 2 (i.e., 16, 64 or 256) QAM trellis code being selected. In response to an odd power of 2 (i.e., 32, 128) QAM trellis code being selected, the respective outputs of the I and Q channel RAMs are input to the remapper RAM, and the remapper RAM output is conveyed via the switch as the trellis demapper output. When an 8-PSK trellis code is selected, the output of the 8-PSK demapper logic network is conveyed via the switch as the trellis demapper output.
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