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Method and apparatus for predicting valid performance of virtual-address to physical-address translations
Method and apparatus for predicting valid performance of virtual-address to physical-address translations
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机译:预测虚拟地址到物理地址转换的有效性能的方法和装置
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摘要
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performace of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.
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