Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

• 1. 逐位逼近延迟锁相环电路及调整输入时钟信号的方法 [P] . 中国专利： CN101764608B . 2012.07.04
• 2. 逐位逼近延迟锁相环电路及调整输入时钟信号的方法 [P] . 中国专利： CN101764608A . 2010-06-30
• 3. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices [P] . 美国专利： US6675311B2 . 2004-01-06

  机译： 数据处理系统从输入时钟生成时钟信号，将其锁相到输入时钟并用于为逻辑设备计时

• 4. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices [P] . 美国专利： US5506982A . 1996-04-09

  机译： 数据处理系统从输入时钟生成时钟信号，将其锁相到输入时钟并用于为逻辑设备计时

• 5. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices [P] . 美国专利： US5388249A . 1995-02-07

  机译： 数据处理系统从输入时钟生成时钟信号，将其锁相到输入时钟并用于为逻辑设备计时

• 1. DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT [J] . Wang Pengjun, Yu Junjun 电子科学学刊（英文版） . 2007,第002期
• 2. DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT [J] . Wang, Pengjun, Yu, 电子科学学刊：英文版 . 2007,第002期
• 3. ANALYSIS OF THE MUTUAL INFORMATION BETWEEN INPUT AND OUTPUT OF A CLASS OF CLOCK-CONTROLLED SEQUENCES [J] . 电子科学学刊：英文版 . 2000,第002期
• 4. Clock synchronization design and evaluation for trigger-less data acquisition system [J] . SHANG Linfeng, SONG Kezhu, CAO Ping 核技术（英文版） . 2012,第006期
• 5. New Real-Time Clock Combines Ensemble of Input Clocks and Provides More Stable Output than Any of the Input Clocks [C] . Wolfgang Klische, Werner Lange Precise Time and Time Interval Systems and Applications Meeting . 2016
• 6. High-speed and multi-bitrate clock and data recovery system based on half-rate clocking [D] . Hong, Sung-Hwan (David) 2005
• 7. Organ specificity in the plant circadian system is explained by different light inputs to the shoot and root clocks [O] . Simon Bordage, Stuart Sullivan, Janet Laird, -1
• 8. Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply [O] . M. Vesterbacka, K. Palmkvist, L. Wanhammar, 2009

• 1. Invariant Modulation of IMF Clock Angle on the Solar Wind Energy Input into the Magnetosphere [J] . HAN Jinpeng ,LI Hui ,TANG Binbin . 空间科学学报 . 2015,第006期
• 2. 利用锁相环时钟生成器实现整数分频本振源设计 [C] . 张杰 ,王兆瑞 . 第二届中国卫星导航学术年会（CSNC2011) . 2011
• 3. 基于电荷泵锁相环的时钟生成电路设计 [A] . 王冬春 . 2009