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Variable length decoder and method for decoding two codes per clock cycle (Variable length decoder and method for decoding two codes per clock cycle)

机译:可变长度解码器和用于每个时钟周期解码两个代码的方法(可变长度解码器和用于每个时钟周期解码两个代码的方法)

摘要

The present invention relates to an apparatus and method for determining the length of a plurality of variable length coded data values contained in a data stream in a single clock cycle. The apparatus includes a shifter for receiving a data stream. The shifter transmits a subset of a plurality of variable length coded data values in response to a shift control signal. The first length decoding mechanism is coupled to receive a subset of a plurality of variable length coded data values in response to a plurality of control signals. The first length decoding mechanism performs a first length decoding operation to determine the length of the first of the encoded data values in the subset. The second length decoding mechanism also determines the length of the second of the plurality of encoded data values. The second coded data value determines the length of the second one of the first coded data values in the subset. The second length decoding mechanism is also coupled to receive a subset of the plurality of encoded data values. The second length decoding mechanism performs a second decoding operation to determine the length of the second of the encoded data values in the subset. The second coded data value immediately follows the first coded data value in the subset. The first and second decryption operations are performed simultaneously. The combined length decoder outputs the combined length of the first and second data values in response to the length of the first and second encoded data values. The shift controller forms a shift control signal in response to the combined length of the first and second data values. The shift control signal identifies the location of the next encoded data value in the shifter. The next coded data value immediately follows the second coded data value. The shift controller sends the signal to the shifter.
机译:本发明涉及一种用于确定单个时钟周期中包含在数据流中的多个可变长度编码数据值的长度的设备和方法。该设备包括用于接收数据流的移位器。移位器响应于移位控制信号而发送多个可变长度编码数据值的子集。第一长度解码机制被耦合以响应于多个控制信号来接收多个可变长度编码数据值的子集。第一长度解码机制执行第一长度解码操作以确定子集中的第一编码数据值的长度。第二长度解码机制还确定多个编码数据值中的第二个的长度。第二编码数据值确定子集中的第一编码数据值中的第二个的长度。第二长度解码机制还被耦合以接收多个编码数据值的子集。第二长度解码机制执行第二解码操作以确定子集中的第二编码数据值的长度。第二编码数据值紧随子集中的第一编码数据值。同时执行第一和第二解密操作。组合长度解码器响应于第一和第二编码数据值的长度来输出第一和第二数据值的组合长度。移位控制器响应于第一和第二数据值的组合长度而形成移位控制信号。移位控制信号标识移位器中下一个编码数据值的位置。下一个编码数据值紧随第二个编码数据值。变速控制器将信号发送到变速器。

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