Checking design for testability rules with a VHDL simulator

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• 3. Checking design for testability rules with a VHDL simulator [P] . 欧洲知识产权局专利： EP0592715B1 . 1997-06-11

  机译： 使用VHDL模拟器检查设计的可测性规则

• 4. Checking design for testability rules with a VHDL simulator [P] . 欧洲知识产权局专利： EP0592715A1 . 1994-04-20

  机译： 使用VHDL模拟器检查设计的可测性规则

• 5. Examination of design rules with a VHDL simulator [P] . 德国专利： DE69220369D1 . 1997-07-17

  机译： 用VHDL模拟器检查设计规则

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