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Data processor in pipeline structure with the ability to decode and execute multiple instructions in parallel.

机译:流水线结构的数据处理器具有并行解码和执行多条指令的能力。

摘要

A pipelined data processor comprises a circuit (3) for extracting two instructions into a pair of instruction registers (l, 2), a circuit (6) for detecting whether those instructions are a combination of an instruction requesting a use of an operation unit and an instruction requesting the use of other resource, and a circuit (4) to control the execution of the instruction when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.
机译:流水线数据处理器包括:电路(3),用于将两个指令提取到一对指令寄存器(1、2);电路(6),用于检测那些指令是否是请求使用操作单元的指令的组合;以及指令请求其他资源的使用,以及电路(4),当检测电路的判断为肯定时,控制这些指令的执行,使得这些指令由操作单元和资源分多个阶段执行。

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