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HIGH VOLTAGE CMOS LOGIC USING LOW VOLTAGE CMOS PROCESS USING A LOW VOLTAGE CMOS PROCESS
HIGH VOLTAGE CMOS LOGIC USING LOW VOLTAGE CMOS PROCESS USING A LOW VOLTAGE CMOS PROCESS
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机译:使用低电压CMOS工艺使用低电压CMOS工艺的高压CMOS逻辑
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摘要
The CMOS transistor logic circuit operates at a high power supply voltage while maintaining the low voltage process by inserting the input shield transistors P1, N1 before the gate terminals of the respective input switching transistors P2, N2. Each shielded transistor has a gate terminal connected to a shielding voltage Vshld that is medium in magnitude between the ground potential and the positive power supply voltage. The input signal is transferred to the switching transistor by the source-drain channel of the input shield transistor.
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