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HIGH VOLTAGE CMOS LOGIC USING LOW VOLTAGE CMOS PROCESS USING A LOW VOLTAGE CMOS PROCESS

机译:使用低电压CMOS工艺使用低电压CMOS工艺的高压CMOS逻辑

摘要

The CMOS transistor logic circuit operates at a high power supply voltage while maintaining the low voltage process by inserting the input shield transistors P1, N1 before the gate terminals of the respective input switching transistors P2, N2. Each shielded transistor has a gate terminal connected to a shielding voltage Vshld that is medium in magnitude between the ground potential and the positive power supply voltage. The input signal is transferred to the switching transistor by the source-drain channel of the input shield transistor.
机译:CMOS晶体管逻辑电路通过在各个输入开关晶体管P2,N2的栅极端子之前插入输入屏蔽晶体管P1,N1来维持低压处理,同时在高电源电压下工作。每个屏蔽晶体管具有连接到屏蔽电压Vshld的栅极端子,该屏蔽电压Vshld的大小在地电位和正电源电压之间。输入信号通过输入屏蔽晶体管的源极-漏极通道传输到开关晶体管。

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