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High performance frame time monitoring system and method for a fiber optic switch for a fiber optic network

机译:用于光纤网络的光纤交换机的高性能帧时间监视系统和方法

摘要

A frame time monitoring system (100) tracks the time in which data frames (11) reside within a fiber optic switch (30) for a fiber optic network. The network switch (30) transfers data frames (11) from source ports (33) to destination ports (33). The frame time monitoring system comprises a digital signal processor (DSP) (100a), which is configured by a software program (108) to implement a plurality of timers (164) relative to frames (11) to be routed through the switch (30) from a source port (33) to a destination port (33). The processor (100a) operates as an incrementer and is configured to output a series of sequential timer states (144) corresponding to each particular frame (11). The timer states (144) are generally indicative of the amount of time in which the frame (11) has resided in the switch (30). A logic network (100b) of logic gates is connected to the processor (100a) to receive and interpret the timer states (144). The logic network (100b) has frame busy (FBSY) and delete mechanisms (204, 207) for determining elapse of respective FBSY and delete time periods based upon the timer states (144). The FBSY and delete mechanisms (204, 207) generate respective FBSY and delete signals (146, 147) after the elapse of the periods, which can vary for optimization reasons depending upon frame class and type. Thus, in the foregoing configuration, a processor (100a) is utilized as a timing incrementer and logical decisions are allocated to the logic network (100b), resulting in an optimum balance between hardware and software so as to minimize cost, space requirements, and complexity, and maximize frame tracking resolution.
机译:帧时间监视系统(100)跟踪数据帧(11)驻留在用于光纤网络的光纤交换机(30)内的时间。网络交换机(30)将数据帧(11)从源端口(33)传输到目的端口(33)。帧时间监视系统包括数字信号处理器(DSP)(100a),该信号由软件程序(108)配置,以实现相对于要通过交换机(30)路由的帧(11)的多个计时器(164) )从源端口(33)到目标端口(33)。处理器(100a)用作增量器,并且被配置为输出与每个特定帧(11)相对应的一系列顺序定时器状态(144)。计时器状态(144)通常指示帧(11)已经驻留在开关(30)中的时间量。逻辑门的逻辑网络(100b)连接到处理器(100a)以接收和解释计时器状态(144)。逻辑网络(100b)具有帧忙(FBSY)和删除机制(204、207),用于基于定时器状态(144)来确定各个FBSY的经过和删除时间段。在周期过去之后,FBSY和删除机制(204、207)产生各自的FBSY和删除信号(146、147),出于最佳原因,这些信号可以根据帧类别和类型而变化。因此,在前述配置中,处理器(100a)被用作定时增量器,并且逻辑判决被分配给逻辑网络(100b),从而导致硬件和软件之间的最佳平衡,从而最小化成本,空间需求和成本。复杂性,并最大化帧跟踪分辨率。

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