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Generic high bandwidth adapter architecture

机译：通用高带宽适配器架构

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摘要

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

机译：通用的高带宽适配器为总线，通道，处理器，交换矩阵和/或通信网络之间的数据通信提供了统一的体系结构。数据由可变长度的数据流分组承载，并且每个分组包括用于调解信息交换的通信协议所需的报头控制信息部分，并且通常包括要被通信的数据的数据部分。通用高带宽适配器包括处理器子系统，该处理器子系统包括用于处理数据分组的报头控制信息部分的处理器。处理器可以访问存储在数据包存储器中的数据包，该数据包存储器存储到达四个通用适配器输入/输出端口的数据包。分组存储器被分成多个缓冲器，并且每个数据分组根据其长度的需要存储在一个或多个缓冲器中。提供了一种通用适配器管理器，用于执行和同步通用适配器管理功能，包括通过在缓冲区中组织数据分组，将数据分组组织到队列中以由处理器子系统进行处理或与通用适配器输入进行传输或从中传输，来在分组存储器中实现数据结构。 /输出端口。每个通用适配器输入/输出端口都与一个包存储器接口相关联，该包存储器接口用于将数据包传送到包存储器中以及从包存储器中传送出去，从而当在输入/输出端口接收到数据包时，数据包被传送到适配器数据包内存并排队等待处理。

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公开/公告号EP0498201A3

专利类型
公开/公告日1996-09-11

原文格式PDF
申请/专利权人 INTERNATIONAL BUSINESS MACHINESCORPORATION;
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申请/专利号EP19920100855
发明设计人 MONTALVO RAFAEL MANTILLA;SEIDMAN DAVID ISRAEL;TANTAWY AHMED NASR-EL-DIN;CHANG PAUL;DELP GARY SCOTT;ZUMBO DOMINICK ANTHONY;MELEIS HANAFY EL-SAYED;
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申请日1992-01-20
分类号G06F13/38;G06F13/40;
国家 EP
入库时间 2022-08-22 03:48:00

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