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Operation mode null of shi -

机译:operation mode null of是 -

摘要

PURPOSE:To facilitate program generation by using three instructions in a branch circuit to constitute a sequence circuit of parallel circuits and performing arithmetic in an arithmetic part of dual stack constitution. CONSTITUTION:A control operation part 1 is provided with an accumulator 2 and a bit accumulator 3. A memory part 4 is provided with dual stack areas 5 and 6 as storage parts of arithmetic data of the accumulator 2, stack pointer storage areas 7 and 8 for areas 5 and 6, and dual bit stacks 9 and 10 as storage parts of arithmetic data of the bit accumulator 3 besides system program and sequence program areas. An input part 11 gives signals of various switches or the like to the control operation part 1, and an output part 12 gives the control signal of arithmetic results to a motor or the like. Since numerical arithmetic and logical arithmetic are performed in the arithmetic part of dual stack constitution, parallel circuits constituting the sequence circuit are compactly constituted.
机译:目的:通过在分支电路中使用三个指令构成并行电路的顺序电路,并在双堆栈结构的算术部分中执行算术,来促进程序生成。组成:控制操作部分1设有累加器2和位累加器3。存储部分4设有双堆栈区域5和6作为累加器2的算术数据的存储部分,堆栈指针存储区域7和8除了系统程序和顺控程序区域之外,用于区域5和6的双位堆栈9和10作为位累加器3的算术数据的存储部分。输入部11将各种开关等的信号提供给控制操作部1,输出部12将算术结果的控制信号提供给电动机等。由于在双堆栈构造的运算部分中执行数值算术和逻辑算术,因此紧凑地构成了构成时序电路的并联电路。

著录项

  • 公开/公告号JP2508702B2

    专利类型

  • 公开/公告日1996-06-19

    原文格式PDF

  • 申请/专利权人 MEIDENSHA ELECTRIC MFG CO LTD;

    申请/专利号JP19870090082

  • 发明设计人 FUJII MASATO;

    申请日1987-04-13

  • 分类号G05B19/05;

  • 国家 JP

  • 入库时间 2022-08-22 03:57:54

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