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Phase simulation ru - pu circuit

机译:phase simulation如 - PU circuit

摘要

A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.
机译:描述了用于使本地数字信号与输入数据信号同步的锁相环。并行相位和频率检测器比较本地信号和输入信号,并生成控制脉冲信号,以控制压控振荡器的频率,该振荡器产生本地数字信号。相位和频率检测器中均包含逻辑电路,用于在检测到输入数据信号的脉冲宽度变长的情况下调整生成的控制脉冲信号,指示在出现输入数据信号不存在或出现双极性冲突中的一种数据信号经过ASI编码。锁相环的特点是输入时间短,输入频率范围大,时钟精确,成本低。

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