首页> 外国专利> DECODER, MPEG AUDIO DECODER, MPEG VIDO DECODER AND MPEG SYSTEM DECODER

DECODER, MPEG AUDIO DECODER, MPEG VIDO DECODER AND MPEG SYSTEM DECODER

机译:解码器,MPEG音频解码器,MPEG VIDO解码器和MPEG系统解码器

摘要

PURPOSE: To obtain an MPEG decoder, which can sufficiently obtain the synchronization of an audio output and a video output. CONSTITUTION: In each of decoders 2 and 3, the reproducing time of each output (audio output and video output) is set based on the decode processing time and SCR and PTS (PTS (A) of audio and PTS (V) of vido) in each decoder 2. The PTS, which is read out of each of registers 11 and 21, is transferred into each of control circuits 14 and 24. The bit stream, which is read out of each of bit buffers 12 and 22, is transferred into each of decode core circuits 13 and 23. In each of the control circuits 14 and 24, the reproducing time of each output is computed based on the decode processing time in each of the decoders 2 and 3 and SCR and PTS. In each of the decode core circuits 12 and 23, each output is formed based on the specifications of MPEG. The reproducing time of each output is controlled based on the result of the computation of each of the control circuits 14 and 24.
机译:目的:获得一个MPEG解码器,它可以充分获得音频输出和视频输出的同步。组成:在每个解码器2和3中,每个输出(音频输出和视频输出)的再现时间都是根据解码处理时间以及SCR和PTS(音频的PTS(A)和视频的PTS(V))设置的从每个寄存器11和21中读出的PTS被传送到每个控制电路14和24中。从每个比特缓冲器12和22中读出的比特流被传送。分别进入每个解码核心电路13和23。在控制电路14和24中的每个中,基于每个解码器2和3以及SCR和PTS中的解码处理时间来计算每个输出的再现时间。在每个解码核心电路12和23中,每个输出是基于MPEG的规范形成的。基于每个控制电路14和24的计算结果来控制每个输出的再现时间。

著录项

  • 公开/公告号JPH08212701A

    专利类型

  • 公开/公告日1996-08-20

    原文格式PDF

  • 申请/专利权人 SANYO ELECTRIC CO LTD;

    申请/专利号JP19940317114

  • 发明设计人 OKADA SHIGEYUKI;YAMAUCHI HIDEKI;

    申请日1994-12-20

  • 分类号G11B20/10;H04L7/00;H04N5/93;

  • 国家 JP

  • 入库时间 2022-08-22 04:03:12

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