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Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed
Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed
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机译：具有粒度提示的虚拟到物理地址转换方案，用于标识要访问的后续页面
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摘要
A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to- register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.
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