PURPOSE:To design the titled circuit that output voltages of two voltage sources appear in a prescribed order without malfunction by providing a constant volt age element connected between a voltage source and other terminal of a switching circuit and a capacitive element connected in parallel with the said voltage source. CONSTITUTION:When an input voltage +Vin is applied from the 1st voltage source 1, transistors (TRs) 17,18 (1st and 2nd switching circuits) keep respectively the off-state. When a negative voltage -Vin is fed from the 2nd voltage source 3 representing a negative polarity, the negative voltage is outputted from an output terminal 6 without any time delay. Since the TR 18 in the off-state is inverted into the on-state to bring the base voltage of the TR 17 to a low voltage, the TR 17 is inverted to the onstate and a positive voltage is outputted from an output terminal 4. Since a positive voltage with a delay time 1 is outputted from the negative voltage output due to a cause such as the switching delay of the TRs or the delay by each resistive element and a stray capacitance, an output voltage attended with a time delay is given between the output terminals 6 and 4 without failure independently of the order of voltage application from the 1st and 2nd voltage sources.
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