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Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays

机译:可扩展的处理器到处理器和处理器到I / O互连网络以及用于并行处理阵列的方法

摘要

A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route- opening packet further includes redundant address bits for imparting a multiple- crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.
机译:公开了一种具有全球路由器网络的大规模并行计算机系统,其中流水线寄存器在空间上分布以提高全局路由器网络的消息收发速度。全局路由器网络包括一个用于处理器到I / O消息传递的扩展分接头,以便I / O消息传递带宽与处理器间消息传递带宽匹配。路由开放消息分组包括协议比特,该协议比特与导向比特被同等对待。路由开放分组还包括冗余地址位,用于向全局路由器网络内的路由器芯片赋予多重纵横制个性。还公开了一种用于在空间上支持大规模并行系统和全球路由器网络的处理器的结构和方法。

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