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Integrating ADC having memory capacitor connected to integrator output and one comparator input and voltage divider connected to integrator output and the other comparator input
Integrating ADC having memory capacitor connected to integrator output and one comparator input and voltage divider connected to integrator output and the other comparator input
An integrating analog-to-digital converter comprising an integrator, a memory capacitor for memorizing the potential of an integrated output from the integrator, a comparator for comparing the potential memorized in the memory capacitor and the potential of the integrated output divided by a set of potential dividing resistances, a clock pulse generating circuit, a counter for counting the period until the integrated output of the reference voltages passes through a reference level using clock pulses, and a reversible counter for counting the period from when the integrated output passes through the reference level to when the integration is completed, by the clock pulses, and for adding its value to the counted value from the counter as low order digits; wherein the number of digits of AD conversion is increased, and high conversion accuracy and high resolution are realized by enlarging the time period from the reference level crossing point to a clock pulse immediately after the crossing in the reference voltage integrating period, and by counting the time using the clock pulses.
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