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High-speed flip flop circuit with master latching circuit free from influence of slave latching circuit
High-speed flip flop circuit with master latching circuit free from influence of slave latching circuit
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机译：具有主锁存电路的高速触发器电路，不受从锁存电路的影响
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摘要
A flip flop circuit comprises a master latching circuit having a first transmission gate responsive to a clock signal and the complementary clock signal for transferring a data bit to a first positive feedback loop, and a slave latching circuit having a second transmission gate responsive to the clock signal and the complementary clock signal and complementarily shifted between on and off states with respect to the first transmission gate for transferring a data bit to a second positive feedback loop, wherein a buffer circuit is coupled between the first positive feedback loop and the first transmission gate so that the master flip flop circuit is free from influence of the slave flip flop circuit, thereby allowing a circuit designer to shrink set-up time margin.
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