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Bistable flip=flop circuit comprising two D=flip=flops and correction circuit - checks output level of first flip=flop and uses correction signal to switch through output of flip=flop or reference signal to second flip=flop
Bistable flip=flop circuit comprising two D=flip=flops and correction circuit - checks output level of first flip=flop and uses correction signal to switch through output of flip=flop or reference signal to second flip=flop
The flip-flop circuit transfers a data signal (DS) depending on a clock signal and includes a first D flip-flop unit (FF1) for receiving the data signal and a first clock signal (CLK). A level tester (PP) checks the output signal (A1) of the first D flip-flop unit to see whether it shows neither of the two states (1 or 0) and produces a correction signal (CHK) if needed. A level correction unit (PK) switches through, depending on the correction signal, either the output signal (A1) or a set reference level signal (BP) as a signal (A1'). There is also a second flip-flop unit (FF2), receiving on its data input the signal (A1') and on its clock input a second clock signal (CLK2) delayed relative to the clock signal fed to the first flip-flop unit. USE/ADVANTAGE - Suitable for asynchronous switching circuits. Setup and hold time of data signal has no undesirable effect on circuit.
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