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SYSTEM FOR PREPARING INSTRUCTIONS FOR INSTRUCTION PARALLEL PROCESSOR AND SYSTEM WITH MECHANISM FOR BRANCHING IN THE MIDDLE OF A COMPOUND INSTRUCTION.
SYSTEM FOR PREPARING INSTRUCTIONS FOR INSTRUCTION PARALLEL PROCESSOR AND SYSTEM WITH MECHANISM FOR BRANCHING IN THE MIDDLE OF A COMPOUND INSTRUCTION.
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机译：用于准备指令并行处理器的指令的系统以及具有在复合指令中间分支的机制的系统。
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摘要
The instruction processor system decodes compound instructions created from a series of base instruction (21) of a scalar machine. The processor geneates a series of compound instruction (33) with an instruction format text having appened control bits in the instruction format text enabling the execution of the compound instruction format text in the instruction processor with a compounding facility (42) which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units (26) of the instruction processor while preserving intact the scaler execution of the base instructions of a scalar machine which were originally in storage. - The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditons, such as branch which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instruction.
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