首页>
外国专利>
Watchdog method for interrupt processing in microcomputer systems - has bistable or counter circuits with logic to combine interrupt request with output to indicate fault
Watchdog method for interrupt processing in microcomputer systems - has bistable or counter circuits with logic to combine interrupt request with output to indicate fault
The interrupt watchdog circuit has a minimum arrangement that consists of a single bistable (BK) with negative logic operation. The reset for the bistable is controlled by an OR gate (1) that receives a service signal (ISERV) and a reset input (RES). The set input (5) receives the interrupt request (IREQ). In order to generate a fault alarm condition the request signal is combined with the output of the bistable in an OR gate (2), such that both inputs have to be low before the alarm (F) is generated. The process may be expanded for multiple inputs via a counter instead of a single bistable. ADVANTAGE - Provides checking of interrupt conditions.
展开▼
