首页> 外国专利> Single-ended sense amplifier with dual feedback and a latching disable mode that saves power

Single-ended sense amplifier with dual feedback and a latching disable mode that saves power

机译:具有双反馈和闭锁禁用模式的单端感应放大器,可节省功耗

摘要

An integrated circuit is disclosed with a logic network having an output coupled to a sense node and having a virtual ground node, and with a sense amplifier having a sensing circuit coupled to the sense node to provide an output signal, charging and discharging feedback circuits coupled to the sense node that limit the swing of the sense amplifier, and an enable control to enable and disable the sense amplifer. In one embodiment in a CMOS integrated circuit a parallel network of n-channel transistors has an output connected to a sense node of a sense amplifier. A sensing inverter and a feedback inverter are connected to this sense node. The switchpoint of the feedback inverter is substantially higher than the switchpoint of the sensing inverter. A charging n-channel transistor is connected between the sense node and a power supply for charging the sense node, and the output of the feedback inverter is connected to the gate of the charging transistor. A discharging n-channel transistor is connected in series between the parallel network and ground. The gate of the discharging transistor is coupled to the sense node. The sense amplifier can enter a power-saving disable mode, and entry is controlled by a sense amplifier enable signal. This mode has two possible states corresponding to the state of the sense amplifier immediately preceding disablement and enables the sense amplifier to avoid output glitches when leaving the disabled mode. The sense amplifier uses two negative feedback loops, including the charging and discharging n-channel transistors, to limit the swing on the sense node, and this swing is substantially independent of the number of parallel transistors that are conductive.
机译:公开了一种集成电路,其具有逻辑网络,该逻辑网络具有耦合至感测节点的输出和虚拟接地节点,以及具有具有耦合至感测节点以提供输出信号的感测电路的感测放大器,耦合的充电和放电反馈电路。连接到限制传感放大器摆幅的传感节点,以及使能和禁用传感放大器的启用控件。在一个实施例中,在CMOS集成电路中,n沟道晶体管的并行网络具有连接到读出放大器的读出节点的输出。感测反相器和反馈反相器连接到该感测节点。反馈逆变器的开关点明显高于感测逆变器的开关点。充电n沟道晶体管连接在感测节点和用于对感测节点充电的电源之间,并且反馈反相器的输出连接到充电晶体管的栅极。放电n沟道晶体管串联在并联网络和地之间。放电晶体管的栅极耦合到感测节点。读出放大器可以进入省电禁用模式,并且进入由读出放大器使能信号控制。该模式具有两种可能的状态,分别对应于禁用之前的灵敏放大器的状态,并使灵敏放大器避免在退出禁用模式时避免输出毛刺。读出放大器使用两个负反馈环路(包括充电和放电n沟道晶体管)来限制读出节点上的摆幅,并且该摆幅基本上与导电的并联晶体管的数量无关。

著录项

  • 公开/公告号US4972102A

    专利类型

  • 公开/公告日1990-11-20

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC.;

    申请/专利号US19890348927

  • 申请日1989-05-08

  • 分类号H03K19/094;

  • 国家 US

  • 入库时间 2022-08-22 05:47:21

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