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Elementary binary counter, synchronous binary counter and frequency divider making use of such an elementary counter
Elementary binary counter, synchronous binary counter and frequency divider making use of such an elementary counter
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机译：使用这种基本计数器的基本二进制计数器，同步二进制计数器和分频器
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摘要
the invention relates to a stable binary counter.;a meter according to the invention comprises a plurality of basic meter mounted in cascade. each meter unit is formed by a half adder having two inputs (ai) (b, c1), an exit "sum" (s1) and an exit "," laughed.the "sum" (if) output is connected to the input of a master - slave switches (m1), the output (qi) is rebouclu00e9e on half adder input (ai). the master and slave systems (mi) (e1) is controlled by two complementary forms (hm and he = mm) of a single clock signal.the exit "(ri) of a half adder (i) is connected to the entrance (b2) of a half adder (a2).;the application of synchronous counters and frequency divider, particularly in the form of a microwave integrated circuit and.
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