A semiconductor memory comprising at least memory cells, word lines (W+, W-), bit lines (BL, &upbar& B) and word line discharge circuits to be co-operated together with a word line discharge current controller. The word line discharge current controller is operative to gradually reduce a word line discharge current absorbed from the word line W- to the word line discharge circuit together with a gradual attenuation of an inverse current from the bit line to the corresponding memory cell.
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