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CMOS gate array with orthagonal gates

机译:具有正交门的CMOS门阵列

摘要

A masterslice semiconductor device comprised of basic cells having additional transistors formed adjacent to the longitudinal end of one or more pairs of transistors which have a configuration almost the same as in the ordinary basic cell. The basic cells are arranged along columns of the semiconductor substrate they are formed in, and constitute a plurality of basic cell arrays. Each of the additional transistors occupies an individual conduction region for the source and drain and is provided with an individual gate electrode which extends to be in line with or perpendicularly to the extension line of the gate of the transistor pair. The additional transistors occupy the space between adjacent basic cell arrays which are, in the prior art masterslice semiconductor device, exclusively used for distributing wiring lines, and accordingly the width of the space is decreased. Because of the versatility of the additional transistors, and the reduced distance between adjacent basic cell arrays, a unit cell can be organized by using the basic cells belonging to adjacent basic cell arrays. The additional transistors are made inactive when the region which they occupy must be exclusively used for distributing interconnecting lines.
机译:由基本单元组成的母片半导体器件,该基本单元具有在一对或多对晶体管的纵向端附近形成的附加晶体管,该附加晶体管具有与普通基本单元几乎相同的配置。基本单元沿着它们形成在其中的半导体衬底的列布置,并构成多个基本单元阵列。每个附加晶体管占据用于源极和漏极的单独的导电区域,并设有单独的栅电极,该单独的栅电极延伸成与晶体管对的栅极的延长线成一直线或垂直于其延伸。附加的晶体管占据相邻的基本单元阵列之间的空间,在现有技术的母片半导体器件中,相邻的基本单元阵列仅用于分配布线,因此减小了宽度。由于附加晶体管的多功能性以及相邻基本单元阵列之间的距离减小,因此可以通过使用属于相邻基本单元阵列的基本单元来组织单位单元。当附加晶体管占据的区域必须专门用于分配互连线时,它们将变为非活动状态。

著录项

  • 公开/公告号US4816887A

    专利类型

  • 公开/公告日1989-03-28

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19870008042

  • 发明设计人 SHINJI SATO;

    申请日1987-01-21

  • 分类号H01L29/78;H01L27/04;

  • 国家 US

  • 入库时间 2022-08-22 06:28:23

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