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NUMERIC VALUE ARITHMETIC CIRCUIT FOR DECODING OF REED SOLOMON CODE OF MULTIPLEX ERROR CORRECTION

机译:多重误差修正的里德所罗门码的数值计算算法

摘要

PURPOSE:To perform numeric value arithmetic calculation with a small circuit scale, by returning the output result of a sum circuit to a product circuit again. CONSTITUTION:An error position alpha sequential generating means 1 generates in order a prescribed number of locations alpha-j (j=1, 2,..., n-1) starting from j=1. Then, a coefficient data selecting means 3 selects one of coefficient data stored in a coefficient data storage means 2 synchronizing with the above generation in a descending order of powers, and sends it to the sum circuit 5 in order. At this time, the alpha-j is multiplied by a value in which 0 that is the output result of the sum circuit 5 is returned first, at the product circuit 4, and 0 is outputted to the sum circuit 5. The sum circuit 5 takes the sum of the said output result '0' and the af, and returns it to the product circuit 4. Then, the product of the output result af and the alpha-J generated by the alpha-j sequential generating means 1 is taken at the product circuit 4, and an output result af alpha-j is sent to the sum circuit 5, and is added on the next coefficient data af-1 selected by the above stated coefficient data selecting means 3, then, a result of afalpha-j+af-1.
机译:目的:通过将求和电路的输出结果再次返回到乘积电路,以小电路规模执行数值算术计算。构成:错误位置α顺序生成装置1从j = 1开始依次生成规定数目的位置α<-j>(j = 1、2,...,n-1)。然后,系数数据选择装置3以幂的降序选择与上述产生同步的,存储在系数数据存储装置2中的系数数据之一,并将其​​按顺序发送给求和电路5。此时,在乘积电路4处将α<-j>乘以一个值,在该值中首先返回作为和电路5的输出结果的0,并且将0输出到和电路5。电路5取所述输出结果“ 0”与af之和,并将其返回到积电路4。然后,输出结果af与由α<-j>产生的α<-> J的乘积。顺序生成装置1在乘积电路4处取,输出结果af alpha <-j>发送到求和电路5,并加到由上述系数数据选择装置选择的下一个系数数据af-1上如图3所示,然后是afalpha -j + af-1的结果。

著录项

  • 公开/公告号JPS63156429A

    专利类型

  • 公开/公告日1988-06-29

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19860304559

  • 发明设计人 OKADA YOSHIYUKI;

    申请日1986-12-19

  • 分类号H03M13/00;G06F11/10;

  • 国家 JP

  • 入库时间 2022-08-22 07:06:06

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