首页> 外国专利> CIRCUIT ARRANGEMENT FOR THE PRODUCTION AND MAINTENANCE OF THE CONTINUOUSLY BETWEEN LOCALLY GENERATED BITTAKTIMPULSEN DERIVED ENVELOPETAKTINIMPULSEN DERIVED ENVELOPETAKTINPULSEN AND IN ENVELOPES ENGLISH BALANCED BALANCES

CIRCUIT ARRANGEMENT FOR THE PRODUCTION AND MAINTENANCE OF THE CONTINUOUSLY BETWEEN LOCALLY GENERATED BITTAKTIMPULSEN DERIVED ENVELOPETAKTINIMPULSEN DERIVED ENVELOPETAKTINPULSEN AND IN ENVELOPES ENGLISH BALANCED BALANCES

机译：局部生成的BITTAKTIMPULSEN衍生的ENVELOPETAKTINIMPULSEN衍生的ENVELOPETAKTINPULSEN和信封中英语平衡余额之间的连续产生和维护的电路安排

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摘要

Circuit arrangement for establishing phase synchronism between clock pulses (T10) and sync bits (S) of data envelopes (EV1, EV2) which in each case contain n bits and are transmitted within the framework of a data signal (D10). The data signal (D10) is delayed by a number of cells of a shift register (SR) and forwarded via a switch (SW) to a comparator which compares bits which are n bits apart from one another with one another and transmits comparison signals (V1) or (V2) which signal defective or, where appropriate, identified synchronisation. A first counter (Z1) counts the comparison signals (V1) relating to the defective synchronisation and, once a predefined counter reading is reached, transmits an error signal (F) to a second counter, which controls the switch (SW) according to its counter readings. IMAGE

机译：用于在时钟脉冲（T10）和数据包络线（EV1，EV2）的同步位（S）之间建立相位同步的电路装置，数据包络（EV1，EV2）分别包含n位并且在数据信号（D10）的框架内发送。数据信号（D10）被移位寄存器（SR）的多个单元延迟，并通过开关（SW）转发到比较器，该比较器将彼此相距n位的位相互比较，并发送比较信号（ V1）或（V2）表示存在缺陷或在适当情况下标识出已同步。第一计数器（Z1）对与同步不良有关的比较信号（V1）进行计数，一旦达到预定义的计数器读数，便将错误信号（F）发送到第二个计数器，第二个计数器根据其控制开关（SW）计数器读数。 <图像>

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公开/公告号ATA11982A

专利类型
公开/公告日1987-05-15

原文格式PDF
申请/专利权人 SIEMENS AKTIENGESELLSCHAFT;
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申请/专利号AT11982
发明设计人
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申请日1982-01-14
分类号H04L7/04;
国家 AT
入库时间 2022-08-22 07:17:40

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