首页>
外国专利>
i med emitterkopplad logik foerverkligad laoskrets som har i med boolealogik foerverkligad ingaongsgrindkrets.
i med emitterkopplad logik foerverkligad laoskrets som har i med boolealogik foerverkligad ingaongsgrindkrets.
展开▼
机译：通过发射极连接逻辑在老挝电路中实现，在输入门中通过布尔逻辑实现门逻辑。
展开▼
页面导航
摘要
著录项
相似文献
摘要
A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.
展开▼
