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Three-input binary adder cell with high-speed carry propagation
Three-input binary adder cell with high-speed carry propagation
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机译：具有高速进位传播的三输入二进制加法器单元
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摘要
A binary adder cell with high- speed carry propagation for three input variables (A and/or A, B and/or B and C or C) and two output variables (R or R, and S or S), produced in accordance with MOS transistor integrated circuit techniques is described. A fast input receives a binary carry element (C or C), and two other slower inputs each receive one of the two other input data elements (A and/or A, B and/or B), these generally being received before the binary carry data. The interval of time between the arrival of these two data elements and the arrival of the carry is used to form the intermediary variable M = A (+) B and its complement M with the assistance of an intermediary calculation circuit which receives these two input data elements, in such a way that at the instant carry C or its complement C arrives, it is necessary to carry out only the following types of calculation: R = AM + CM or R = AM + CM and S = CM + CM or S = CM + CM. IMAGE
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机译：二进制高速加法器单元将根据以下公式产生的三个输入变量（A和/或A，B和/或B和C或C）和两个输出变量（R或R和S或S）进行传播。描述了MOS晶体管集成电路技术。快速输入接收二进制进位元素（C或C），另外两个较慢的输入每个接收其他两个输入数据元素（A和/或A，B和/或B）之一，这些通常在二进制输入之前接收携带数据。在接收这两个输入数据的中间计算电路的辅助下，使用这两个数据元素的到达与进位的到达之间的时间间隔来形成中间变量M = A（+）B及其补码M元素，使得进位C或其补码C到达的那一刻，仅需要执行以下类型的计算：R = AM + CM或R = AM + CM且S = CM + CM或S = CM + CM。 <图像>
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