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Switching suppression circuit for pulse radar receiver - uses clock circuits and logic circuits to obtain time interval for phase cancelling signals
Switching suppression circuit for pulse radar receiver - uses clock circuits and logic circuits to obtain time interval for phase cancelling signals
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机译：脉冲雷达接收机的开关抑制电路-使用时钟电路和逻辑电路来获取相抵消信号的时间间隔
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摘要
The procedure eliminates parasitic signals which are generated from the switching of the receiver channels in a radar station by double switching with a defined time interval. The parasitic signals from each switching action are in phase opposition and readily cancel. A switching control circuit is provided and uses two precise clock circuits to generate a time interval via logic circuits and an OR gate. The second clock is controlled from a summing circuit which receives transfer function signals from corrector circuits. Supplementary switches generate parasitic signals which pass via a mixer to control the second clock in a control loop. This loop is broken by a switch if the parasitic signal is outside the range of the receiver filter.
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