首页>
外国专利>
Priority interrupt apparatus employing a plural stage shift register having separate interrupt mechanisms coupled to the different stages thereof for segregating interrupt requests according to priority levels
Priority interrupt apparatus employing a plural stage shift register having separate interrupt mechanisms coupled to the different stages thereof for segregating interrupt requests according to priority levels
A priority level controlled unit for use in a microprogrammed digital data processing system for handling interrupt requests from interrupt sources having different interrupt priority levels. Each interrupt request is a plural-bit request having a priority level field and an interrupt source identifying field. A plural stage shift register is provided, each stage having enough bit positions to hold a single interrupt request. Successive shift register stages are assigned to successively lower priority levels. The interrupt requests are supplied one at a time to the highest priority level stage in the shift register. A separate comparator mechanism, coupled to each shift register stage, compares the priority level field of an interrupt request residing therein with the priority level value assigned to such stage for indicating priority level matches and mismatches. If a priority level mismatch is indicated for any given stage, then the interrupt request therein is transferred to the next shift register stage. A separate first- in-first-out storage stack is associated with each stage. If a priority level match is indicated for any given stage, then the interrupt source identifying field of the request producing the match is stored into the storage stack for such stage. A separate instruction address mechanism, coupled to the output of each storage stack, responds to the currently output interrupt source identifying field for developing an appropriate interrupt routine address pointer. This pointer is transferred to the data processor control store for initiating execution of the appropriate microcode interrupt routine provided that a valid interrupt request is not pending in the storage stack for a higher priority level. If any higher priority level requests are pending, then the transfer of a lower level address pointer to the control store is blocked until such higher priority level requests have been serviced.
展开▼
